1. Field of the Invention
This invention relates to bus architectures and particularly to a priority bypass bus which provides minimum latency for priority data channels.
2. Description of Related Art
A bus is a communication path between various devices of a electronic system. For example in a computer system, the central processing unit (CPU) communicates with main memory through a memory bus. Peripheral devices may also be connected to the memory bus or connected to the CPU through a separate IO bus.
Buses can be divided into two general categories: point-to-point buses and shared buses. A point-to-point bus connects only two bus devices together. A shared bus can be used by more than two bus devices. Thus the number of buses required for communication depends on whether point-to-point or shared buses are used. For example, four bus devices require six point-to-point buses to communicate with each other, but four bus devices can communicate through a single shared bus. With a shared bus architecture, all four bus devices can share a single bus.
Point-to-point buses have the advantage of lower latency, minimal bus contention, and the ability to support multiple simultaneous data transfers. However, the large number of buses used in a point-to-point bus architecture require a large amount of chip or board area.
Since only a single shared bus can support multiple bus devices, the chip or board area required to implement a shared bus architecture is much less than is required by a point-to-point bus architecture. With the increasing complexity of electronic systems, data buses have increased in width. Wide data buses preclude the use of many point-to-point buses when chip or board area is costly. Therefore, shared buses are commonly used in complex electronic systems.
A major disadvantage of the shared bus is a high bus latency, i.e., the time between a bus device requesting use of the bus and the bus device being able to use the bus. A major source of bus latency in a shared bus occurs if multiple bus devices require the bus simultaneously.
Bus latency is increased if multiple bus devices request communications with the same target bus device. In such a situation, the target bus device may queue several requests and respond to each request in turn. Therefore, the later request to the target bus device suffers a greater latency. Therefore, a bus system is desired which provides low latency but does not consume the area consumed by a point-to-point bus architecture.